Driven by the advancement of applications such as power amplifiers, RF semiconductors, and high-speed solid-state drives (SSDs)—which increasingly require compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN)—custom substrates are increasingly being employed. Intelligent design and developments leveraging advanced substrate materials are essential to success.

Each substrate type has unique properties and benefits to accommodate microelectronics device requirements. This can make design and development quite time-consuming. Besides being costly, prolonged processes are disadvantageous when coping with time-to-market (TTM) pressures. To avoid this complication, companies need a team of substrate experts who can quickly deliver small-volume packaging and assembly solutions featuring custom substrates.

Unique Substrate Requirements Require Customized Approaches

In 2021, Mixed-Signal Devices (MSD) came to QP Technologies for help in developing  complex packages required for their newest clock technologies that comprised multiple components, a multilayer substrate, overmolding, underfill, and other features. MSD customers in the aerospace and defense industries have three key supplier requirements: they must be domestic, meet International Traffic in Arms Regulations (ITAR), and be capable of quick lead times. QP Technologies met these requirements, producing six substrate designs and 30 builds, with excellent quality and cycle times, spanning only 18 months. As a result, MSD was able to release its flagship family of MS11xx oscillators with the highest performance in the industry, with exceptional TTM.

Saving Time and Money – From Substrate Design to Assembly

Another customer in the IP space, looking to avoid a complete redesign of their assembly, approached QP Technologies for our substrate design and manufacturing expertise. We were able to develop an entirely new substrate for a complex flip-chip assembly, thus preventing a costly redesign. Once again, the priority was delivering low volumes of high-quality assemblies within a short timeframe. The customer’s existing IP core test system was valued in excess of $500,000 and would have taken more than eight months to redesign. Rather than create a completely new assembly, QP Technologies saved the customer time and expense by facilitating the use of their legacy platform through an interposer-based solution. The entire project was designed, built, and assembled in under four weeks at just 10-15% of the cost of developing an entirely new assembly.

A Host of Substrate Services for a Range of Markets

QP Technologies’ substrate design, fabrication and development services fill technology gaps that standard, off-the-shelf solutions cannot. Customers increasingly leverage QP Technologies for quick-turn, small-volume custom substrate solutions for advanced applications with high-power and speed requirements; for IP verification; and for creation of test boards and samples.

QP Technologies offers comprehensive services for custom substrate development, from design to fabrication and assembly. Our combination of quality, variety, and speed meets the demands of various markets, including military, medical, and sensors. Our domestic fab and cost-reducing approach provides convenience and efficiency. Most importantly, our dedicated team is passionate about working closely with customers on their unique chip designs and finding the best solutions for the most complex requirements.

If you would like to explore our substrate capabilities, visit our website at https://www.qptechnologies.com/products/substrate-development/ and learn more about our experience with custom substrates by downloading our latest whitepaper: https://www.qptechnologies.com/custom-substrates-expertise/

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Medtech and biotech devices are uniquely suited to benefit from emerging electronic capabilities – specifically, the kind of electronics design, packaging and assembly offerings that are Promex’s specialty. With that said, these markets present a variety of manufacturing challenges and demands that require heterogeneous integration (HI) to address.

This two-part blog post provides a high-level overview of the current HI environment, including:

• Convergence of medtech and biotech with electronic and non-electronic content;
• How to pursue manufacturing and assembly of converged devices;
• HI project development and case studies; and
• Factors to consider when selecting a contract manufacturer.

Technology convergence

As the medical and biotech industries have evolved over the years, mankind has benefited from an ever-broadening range of capabilities, from new medicines and vaccines to advanced surgical techniques and DNA sequencing, to name a few. Information technology (IT) has continued to evolve in parallel with these advancements, making what was once the stuff of science fiction part of our everyday lives – with the integrated circuit and network connectivity helping to fast-track technology innovation.

Today’s environment represents a growing convergence of medicine and technology. New functionalities require a combination of electronic and non-electronic/mechanical content, such as high-power devices for automotive applications or adding flexible circuitry to traditional medical devices. This creating new manufacturing and assembly challenges that have given rise to HI assembly techniques.

What is HI assembly? Put simply, it’s a manufacturing approach that combines electronic and non-electronic content in devices to enable a range of complex functionality. Being well-versed in the convergence of medical and biotechnologies with microelectronics, Promex can engage with you to ensure that you know a) what you need for your project, and b) how to get there. This means determining what non-mechanical parts to use, developing a process to integrate all of the parts together, and building the devices in batches to ensure their functionality. Multiple steps are involved at each phase, as you can see in the heterogeneous assembly process illustration shown in Figure 1.

Manufacturing converged devices

Let’s take a look at some of the specifics of how devices transition from concept and prototyping to production. Traditional assembly follows a standard trajectory of process steps (Figure 2a) but isn’t designed to accommodate unique components and chemistries, and their associated challenges, that are integrated into the project design when dealing with converged HI devices.

For example, MEMS devices combined with a gyroscope are highly sensitive to touch and electrostatic discharge (ESD); power devices, which control multiple kilowatts of power, have issues with thermal conductivity and high voltages; and flexible circuitry that enables flexible devices has unique assembly requirements to accommodate its high tolerances.

Figure 2b shows an adapted process that utilizes HI assembly techniques for converged devices. In this process, unique, non-electronic parts are added to the assembly at various stages based on their properties and preparation requirements – e.g., if holes must be taped to protect fluid content or if die-attach film (DAF) must be applied for ease of location.

In the second part of this post, we will share some case studies of medical devices developed using HI assembly techniques, as well as tips for selecting the right contract manufacturer to meet your requirements.

The post Enabling New Functionality in Medtech and Biotech Devices appeared first on QP Technologies.

Cost and performance are the two most pressing issues in chip design and manufacturing. Chiplets are a key solution being pursued by the semiconductor industry to help mitigate these challenges. These small die with specialized functionality are designed to be combined to make up a larger device, following the industry trend of heterogeneous integration. In this post, we’re going to look at some of the challenges associated with assembling and packaging these complex devices – specifically, exploring optimizing chiplet packaging for complex applications. 

With packaging technology poised to play a key role in the performance of next-generation systems, chiplets are emerging as one the most hotly pursued solutions. Chiplet-based designs can use a wide range of materials, and this single-package integration allows efficient integration of multiple silicon die using high density substrates, silicon interposers, bridges and other interconnect methods.

The rise of the chiplet era yielded creation in 2018 of the Open Compute Project’s (OCP) Open Domain-Specific Architecture (ODSA) subproject, which is focused on defining and developing a chiplet-based architecture and die-to-die interfaces. Built to address die disaggregation and IP reuse, ODSA supports efforts to advance an open chiplet ecosystem. Its charter includes addressing design and industry collaboration challenges, as well as staying on top of such questions as:

• What chiplets are available – details, datasheets, other information
• Vendors/sources for interposers – capabilities, delivery times, pricing
• Interposer delivery times – chips typically require measurement and custom interconnect; with chip-on-interposer technology, the die and interposers can be fabricated in parallel

One of the first chiplet approaches utilized two chiplets – a high-bandwidth memory (HBM) and an ASIC/CPU – on a substrate with passives and high-density interconnects. Included in this scheme was a solder bump “bridge” embedded in the PCB to electrically connect the two chiplets. A more recent, more complex 2.5D/3D scheme uses a silicon interposer on the circuit board with a ball grid array (BGA) on the back and high I/O count. Typically, an ASIC or CPU is mounted in the center with high-bandwidth memory (HBM) die on either side, all interconnected using one of several schemes, described below.

Typical chiplet packages and interconnects

There are a few different methodologies for packaging chiplets, each of which comes with its own set of requirements. Each chiplet has a first, or ‘top’ surface and a second, or ‘bottom’ surface. Common connection methods include flip-chip with solder bumps, copper pillar with solder reflow, and hybrid, i.e., die on silicon interposer, using silicon oxide for the dielectric and copper for the bonds. Multiple substrate types can be employed, such as classic or fine-line PCBs, silicon or glass interposers, or interconnect built in-situ using a redistribution layer (RDL)-like process.

“Chiplet-last” describes a process by which the chiplet die are first bumped and then attached to a substrate or interposer. Flip-chipped onto a PCB is a common approach, as it is also often used with bare die. Figure 1a shows an example of a classic flip-chip on PCB uses a glass-epoxy core with only epoxy on the outer dielectric layers. Bumps are added to the die using conventional solder, and the die are underfilled to add mechanical strength.

A more advanced approach, shown in Figure 1b, is for two or more chiplets to be attached directly to a substrate. Substrate examples include an n-N-n PCB structure, glass-epoxy core, ABF build-up film interconnect dielectric, with ENIG (nickel + gold) on the substrate surface, with small (25-50µm) lines and spaces, and area of <100×100 mm. Copper pillars with ≤129µm pitch on the die are usually used. All of this taken together illustrates a step up in density for this approach.

The next layer of sophistication for a chiplet-last approach is mounting the chiplet on a silicon interposer and then utilizing solder reflow (Figure 2a) to form the interconnects. With copper pillars you can use dielectric materials such as silicon oxide, polyimides or BT to build up a much higher-density interconnect structure. You can get down to 5 micron lines and spaces in an area of 35x35mm or less.

Hybrid bonding (Figure 2b) requires a very flat substrate with SiO₂ and copper in the interconnect. The die is carefully placed and then bonded to the substrate using heat and pressure. This process enables fairly large, robust structures to be built, potentially using solder balls and through-silicon vias (TSVs) or by wire bonding from the top surface of the silicon interposer to a conventional PCB.

By contrast, the “chiplet-first” method is an RDL-like process. The chips are mounted with the active surfaces placed face-up, exposing the contact surfaces of all the chiplets and components well planarized. This process requires accurate location of connection points or an active patterning method to ensure connections are made to the chiplet contact area when die locations vary from site to site.

The interconnect is built with conductor and dielectric deposition and patterning steps, involving multiple copper interconnect layers, polyimide or epoxy dielectrics, and conductor-layer-to-conductor-layer microvias. For higher layers, lithographic masks can be used, but laser patterning can also suffice. Laser patterning is particularly useful when the pattern of the interconnect has to be modified from wafer to wafer due to small variations in die location.

Table 1 summarizes the key features associated with each of the methods for optimizing chiplet packaging discussed above, along with cost and time-to-market parameters. Some are further along in development and implementation than others, but all require, or will require, capabilities such as those offered by QP Technologies.

As part of our proven assembly expertise, we offer a range of die bonding services essential to chiplet processes, including flip-chip, die attach, die-attach film (DAF), thermocompression, epoxy dispensing, and die stacking. Moreover, through our substrate development service, we can develop solutions leveraging advanced laminates such as FR-5, BT and ABF.

To learn more about our capabilities and get started on optimizing chiplet packaging, click here.

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QP Technologies recently exhibited at the first Chiplet Summit, held January 24-26 in San Jose, California. Dick Otte, CEO of our parent company Promex Industries, participated on a panel titled “Best Packaging for Chiplets Today.” Moderated by Nobuki Islam with JCET Group, the packaging panel also included Daniel Lambalot, Alphawave Semi; Laura Mirkarimi, Adeia; Syrus Ziai, Eliyan; and Mike Kelly, Amkor Technology.

In attendance was longtime semiconductor industry analyst and pundit Dean Freeman. Dean kindly shared with us some highlights and comments that emerged from the discussion for this guest commentary. (Photo courtesy of Rosie Medina, QP Technologies VP of sales & marketing.)

1. Does the chiplet packaging solution violate Moore’s Law?

Moore himself had allowed for the fact that it might prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. While the packaging of chiplets is definitely moving into the third dimension, this aspect of chip manufacturing is covered under Moore’s Law. The chiplet is essentially a continuation of the trend toward greater functionality per unit volume that has taken place over time. Moore established a vision for the industry, and chiplets are the next evolutionary step. Because leading-edge device dimensions are now down to a few atoms, we need to go to 3D. 

2. What are the key chiplet packaging challenges?

There are multiple challenges to chiplet and 3D packaging.  Multi-chiplet design tools, thermal management, interposer choices, interconnects methods such as through-silicon vias (TSVs), flip-chip, hybrid bonding, bumping, and testing, especially of individual chiplets and at intermediate assembly stages. Standards will help alleviate some of the challenges, but it will come down to meeting the customer requirements in an economical manner.  

3. Is IP an issue for the chiplet package when we deal with designs from various sources to integrate the chiplet?

The design challenge for AMD and Intel is different than for smaller companies. Elements of design and integration are easier, as they design and build most of the parts in the package. Smaller companies, on the other hand, need to buy off-the-shelf parts and design the interposers and packages, so there will need to be a logic and functional specification for the chiplets. A unified platform might be helpful, but the industry needs to work through the standards to develop that platform.  A de facto standard might arise due to designers adopting immediately available chiplets and the required immediate manufacturing need. 

4. The business model for chiplets is highly dependent upon market size; we may need an ecosystem and infrastructure investment to support a robust service for chiplets. Will the market be big enough to justify the investment?

From the amount of activity surrounding 3D packaging, the larger companies are already investing at a significant rate. Growing new capacity without revolutionizing the manufacturing lines will be an important aspect of growing the business profitably. There will need to be a long continuum of adoption as the industry shifts to finer lines and smaller pitches that will enable the industry to invest so the segment can grow quickly, but also expand for the long haul. Some technologies, such as embedded bridges, may be more challenging for broad industry implementation.   

5. Hybrid bonding is being used by some of the key fabs for wafer-to-wafer bonding. Do you think this will be adopted by OSATs? 

The consensus is that OSAT will adopt hybrid bonding, as it is one of the ways to keep shrinking the package and reducing parasitics.

6. What’s next after hybrid bonding?

Hybrid bonding will be with the chiplet space for a long time. 

7. What areas should we focus on for a shorter time-to-market for chiplet packaging?

The industry needs to get good control over all the parts needed to put the system together. To get to a shorter time to market, better design tools are needed that allow you to figure out how to glue them together so that you know how to partition the chips, and how to do interconnect for both chip first and chip last approaches. Also, reducing the time and cost to deliver new interposers is important.

8. Are the existing design/simulation tools capable enough to meet chiplet design requirements? 

It appears that the majority of the tools needed are in place to make this happen, but the designers need to catch up.

9. What area do you think software design companies need to focus on to improve their chiplet capabilities? 

The software companies need to develop a higher level tool that will support integrating multiple die/chiplets and enable the design of the interposer or interconnect structure. A move to silicon and maybe glass from organic dielectric interposers may be necessary to improve reliability, provide the interconnect density for interposers. 

10. What other improvements need to be made to our supply chain ecosystem to support future demand? 

Do what is practical for today. Develop test vehicles and get manufacturing going.  If common interfaces can be developed that everyone can qualify to, which includes not having to redesign legacy chips, then the industry can start moving forward in a meaningful way.

The post Panel Tackles Chiplet Packaging Challenges appeared first on QP Technologies.

MIL-STD-883 is the military testing standard that determines uniform procedures and methodologies for testing microelectronic devices. It’s designed to identify devices suitable for use within military and aerospace electronic systems – i.e., those that can survive harsh natural environments and conditions.

The full standard defines a comprehensive range of processes and procedures. As part of our collaboration with our customers in this market, QP Technologies will assist with the management your circuit qualification per the MIL-STD-883, Method 5004 process flow. Method 5004 falls under Test Procedures – specifically, parts qualification and lot screening. The diagram below illustrates a typical Method 5004 flow that customers utilize to qualify their parts, for both Class B and Class S process steps.

Some devices require full blown qualification flows, and others only require some of these tests be pulled into your flow to ensure a robust device.  Ultimately, the purpose of all screens conducted within MIL-STD-883 is to ensure testing, manufacturing, and materials uniformity – in turn, ensuring consistent quality and reliability among all devices screened in accordance with the schedule.

To discuss your mil-aero project scope and requirements with us, click here, or call 858-674-4676.

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The Hesse BJ939 performs bonding for Al heavy wire and ribbon, as well as copper (Cu) and AlCu wire. The heavy wire bond head features improved wire handling, advanced looping capabilities, and the ability to perform non-destructive pull tests on bonds in real-time. Our heavy wire Al wedge bonding capabilities include 127µm (5 mil), 254µm (10 mil), 381µm (15 mil) and 508µm (20 mil) diameter wire.

The basic functionality of the tool is that Al wire is situated beneath the tool and brought to the surface at a constant velocity. Upon touchdown, ultrasonic power is applied, and the bond tool’s vibration softens both the wire and the surface, enabling them to bond together via shared electrons. No heat is generated during the process, and no post-cleaning is required after the bond has been made.

Being able to perform this advanced Al wire wedge bonding with the BJ939 allows us to work with customers needing this capability for power electronics in a range of military-aerospace, automotive, consumer and industrial devices. Power electronics also play an important role in the field of renewable energy. We look forward to continuing to grow our business in these vital areas.

The post Aluminum Wire Bonding Key for Power Electronics appeared first on QP Technologies.

The show organizers reported a total of 514 registered participants. About 275 attendees gathered in person to view industry experts presenting keynotes and technical sessions, most of which took place onsite, with some live-streamed. While overall traffic on the exposition floor was definitely lighter than we would have seen pre-pandemic, quality trumped quantity. The people that we talked to were decision makers for their companies, and several made the trip to our facility to take a tour and see how we’re  satisfying customer demand. The positive response and discussions left us enthusiastic about what may result from these interactions.

A key aspect of the surge in business that we’ve experienced of late has been our ability to meet customer demand during the pandemic. Interruptions in the supply chain have created difficulties for many of those relying on offshore packaging and assembly firms. As a long-established U.S.-based provider of these capabilities, as well as wafer preparation and custom substrates, we have been able to quickly jump in and accommodate demand. These engagements have opened up new opportunities that will help propel us forward as we continue expand our technology offerings.

The post iMAPS 2021 Recap – A Great Show appeared first on QP Technologies.

The acronyms involving funding for semiconductor manufacturing are flying around Washington. There is the Chips for America Act, focused on re-shoring, The Facilitating American-Built Semiconductors (FABS) Act that promises tax credits for investments in, either equipment or fabs. and then there’s the $250 billion US Innovation and Competition Act, which earmarks $52bn for new chip manufacturing and research. This is now being debated in the House of Representatives. There’s a lot to unpack here – what we’re focusing on today is how all of this could impact advanced packaging and test in the US – To talk about this, we invited 3D InCites Community Members. Bob Patti, of Nhanced Semiconductor, Alan Huffman, of Micross Components, and Dick Otte, of QP Technologies. 

The conversation covers a wide range of questions: Will the $52Bn be enough? How should those funds be best allocated? What will the impact be on small entities? Where will the workforce to support it come from? How do we create a US supply chain? Are we politicizing chip manufacturing? How do we ensure that Foundry 2.0 adds IP value and attracts new talent? Is the answer a vertically integrated advanced packaging company?  Should we create a consortium of advanced packaging companies and use the government funding to fill in the gaps? 

 Tune in to hear the answers to these questions and much more. 

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Few things can snap your priorities into focus like the onset of a pandemic. Our industry is known for its cyclical nature, so adapting to change is not a new concept. But dealing with the challenges posed by COVID-19 has been like nothing any of us have experienced before.

QP Technologies has been fortunate to weather the pandemic well – less than 0.05% of our staff has tested positive, with the first case not emerging until December and, thankfully, none being serious. Due to the efforts of our entire team, we have actually grown the business by nearly 15% over the past year and added new hires to help meet the demand for our services. Some key actions have seen us through this challenging time.

Our first priority was staff and customer safety. As soon as the quarantine was imposed, employees able to work remotely (including our entire sales staff) shifted to work-from-home mode. We provided necessary equipment, such as upgraded laptops and peripherals, and updated training on web-sharing software as needed, to ensure they could do their jobs effectively.

Once we secured our designation as an essential business – gathering letters from customers stating we were vital to supporting their own essential businesses – we put in place measures to ensure our adherence to state and county guidelines for remaining operational. We retained a crew to clean high-touch points in our Escondido facility throughout the day and thoroughly clean each night; we propped open interior doors wherever possible to minimize contact and improve air circulation; and we installed hand-sanitizer dispensers throughout the building. Of course, we also mandated the use of face masks and temperature checks for employees and (limited) visitors.

Despite these measures, some team members in positions that require onsite presence were uncomfortable coming into the facility and ultimately decided not to return to work. We respected their concerns and allowed them to depart. To fill their positions safely, we held first-round interviews by phone and subsequent interviews virtually. Only serious candidates we planned to hire were brought into the office, with a minimal number of people allowed in the meeting room.

Remote but not removed

During the pandemic, we’ve found viable workarounds for a number of tasks that would have been accomplished in person before. For example, when we’re developing a prototype, we often find customers want to see their devices during manufacturing; to view how special components of their device are being processed; and to resolve any process-development issues.

To keep the quantity and length of customers’ onsite visits to a minimum, we’ve utilized a creative approach: our team has been using GoPro cameras to provide customers with remote visual access to critical process steps.  This solution prevents the customer from having to physically visit the factory, and it’s allowed us to effectively troubleshoot and resolve issues in real time without having to wait for a site visit. We anticipate some customers continuing to use this approach, particularly international customers for whom onsite visits are challenging even without the pandemic travel hurdles.

Internally, we’ve streamlined and moved online as many processes as possible, such as getting purchase request forms signed and processing quality documents such as ECN’s electronically. We have also shifted our ISO audits to a virtual process, using internet web hosting sites and iPads on rollers to walk the floor and share documents for proof of evidence.

A key challenge throughout the pandemic has been maintaining customer relationships without holding face-to-face meetings, especially for those who prefer not to meet on-camera. Over the past year, without having live tradeshows as an opportunity to meet, we’ve placed more emphasis on picking up the phone to stay in touch, as well as reaching out via social media and attending virtual events. On a positive note, the quality of content at virtual shows has provided ample opportunity for continued learning and keeping up with industry developments.

Staying healthy, in all ways

It’s important to note that we’ve kept close tabs on how our team members have been coping mentally and emotionally. Burnout from the convergence of work and home environments is a very real concern, so we’ve increased our emphasis on maintaining balance, encouraging people to keep set hours and avoid working longer than necessary. Through our insurance plan, counseling resources are available to any employee who needs it, including free remote sessions.

As vaccines become more widely available, things are opening up, and people are starting to feel safer about going out in public or just seeing friends and colleagues in person. We look forward to being able to have all our team members together when we are “back to normal” post-pandemic, but we will not forget the lessons we’ve learned about our resourcefulness and resilience in the face of adversity.

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A new year always brings the promise of a fresh start, a chance to reset, reinvigorate and perhaps refocus goals and objectives. This may never have been truer than when 2021 arrived.

In February 2020, we moved our operations into our new, wholly owned headquarters in Escondido, California, a few miles away from our former facility. This allowed us to optimize our production line, improve efficiencies, and take on new, more complex projects – never dreaming of what was just around the corner.

Although our company has been able to continue operating as an essential business throughout the past year – in turn, helping enable our customers to sustain their own production – we’ve remained ever mindful of the human toll and personal challenges that the COVID-19 pandemic has brought about for so many.

With that said, we entered 2021 with strong optimism for the year ahead, and this week we have implemented a change that was a long while in the making. Quik-Pak is now QP Technologies – a new name chosen with the needs of our customers in mind, to reflect that we offer you the best of two worlds.

As Quik-Pak, we became known for fast-turn, cost-efficient, “under one roof” services that have allowed us to be a trusted resource for your wafer preparation, chip packaging and assembly needs for more than 20 years. Helping you get your products to market quickly and efficiently remains our highest priority.

As QP Technologies, we are building on this foundation by combining our proven know-how with expanded capabilities. We’ve developed innovative technology that we’re implementing in new ways so that we can offer products and services that meet your growing needs – both immediate and emerging – while continuing to provide high quality and fast delivery.

Big-name chipmakers are building up their U.S. fab capacity, which will heighten demand for onshore packaging and assembly offerings – in turn, creating new opportunities for QP Technologies in the coming year and beyond. Our established position as a leading U.S.-based packaging and assembly provider is an advantage for our customers, as working with us enables them to lessen the risks associated with offshore supply-chain providers. We will be talking about this more as the year progresses. 

Overall, the year ahead is likely to be a strong one for the industry and for our business. We look forward to working with our customers and partners to help make this prospect a reality.

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